This invention relates to data processing systems and more particularly to the use of memory storage subsystems employing memory storage elements which are accessed in a serial rotational fashion.
The use of memory storage elements with serial rotational characteristics has been known for some time. Many different electromechanical and semiconductor technologies have produced memory storage elements which exhibit some of the same functional characteristics. The common characteristic of concern, herein, is the serial rotational nature of these storage elements which may be defined as the tendency of each sequential cell to move in time functionally (and perhaps physically) to and away from the memory storage element access point in a cyclic manner. This tendency makes the average length of time required to access a given cell dependent upon the rotational speed of the memory storage element. The length of time required to make one complete rotation is called cycle time. The average length of time required to access a given cell because of this tendency is called average latency. Since it is desirable to minimize average latency, it has been common in the art to increase the rotational speed (i.e., decrease the cycle time) of the memory storage element. It should be added that increasing rotational speed is not without its practical limits as this causes increased input power requirements, increased physical and electrical component stress, and decreased signal-to-noise ratio.
An increase of rotational speed also decreases the transfer time, as transfer time is the length of time it takes the memory storage element to rotate from access to one cell to access to the next sequentially addressable cell. It was found in many cases that rotational speeds causing desirably low average latency within acceptable power, stress and signal-to-noise ratio ranges, produced transfer times sufficiently low as to tax the Input/Output (I/O) capacities of the accessing mainframe computer referred to herein as the Central Processor Unit (CPU). Transfer times which are too low also produce priority conflict problems amongst I/O devices.
The common technique used to solve the problem of insufficient transfer time at desirable rotational speeds is called interlace. Interlace is a recording method wherein the cells found physically sequential within the memory storage element are not addressed sequentially by the Central Processor Unit (CPU). A very simple example might be the sequential addressing of every second physical cell within the memory storage element, called two-to-one interlace. This would provide double the transfer time without affecting the rotational speed and, therefore, the average latency.
The interlace method adapted for a given application may sequentially address every third, fourth, or nth physically sequential storage cell, depending upon the desired relationship between rotational speed and transfer time.
Present art normally utilizes interlaced serial rotational memory storage elements by having the CPU transfer an address identifying the first cell within a sequentially addressable block of cells to the memory storage subsystem which begins transferring the requested data at such time as that addressed first cell rotates past the memory storage element access point. If the requests from the CPU are truly random addresses made at times asynchronous to the cycle of the memory storage element, the average latency becomes one-half the cycle time of the memory storage element.
The present invention lowers this effective average latency experienced by the accessing CPU by permitting the transfer of the requested data block from any (rather than just the first) cell within that block by providing an apparatus that forecasts the address of the first cell to be transferred.